1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage apparatus such as a NAND flash memory.
2. Description of the Related Art
An electrically-rewritable flash memory has been known a semiconductor storage apparatus. Particularly, the high integration of a NAND flash memory including a NAND cell block having serially connected multiple cells is widely noticed.
One memory cell of the NAND flash memory has a FETMOS construction in which a floating gate (charge accumulating layer) and a control gate are stacked through an insulating film on a semiconductor substrate. A NAND cell unit includes multiple memory cells, the adjacent memory cells of which are serially connected by sharing the source and drain. The memory cell array includes NAND cell units arranged in a matrix.
The drains of the memory cells on one end of the NAND cell units aligned in the column direction of the memory cell array are commonly connected to a bit line through selected gate transistors, and the sources of the memory cells on the other end side are connected to a common source line through the selected gate transistors.
The word lines of the memory cell transistors and the gate electrodes of the selected gate transistors are commonly connected thereto as word lines (control gate lines) and selected gate lines in the direction of the row of the memory cell array.
The NAND flash memory has been disclosed by Non-Patent Documents 1 and 2 mentioned below, for example.
Non-Patent Document 1 describes an operation of a NAND flash memory, but the details will be described with reference to FIGS. 1 and 2.
FIG. 1 is a circuit diagram showing a construction example of a memory cell array of a NAND flash memory. FIG. 2 is a diagram showing bias states of erasing, reading and writing operations on a NAND flash memory.
The NAND flash memory in FIG. 1 includes a memory cell array 2 having multiple memory cell units 1-0, 1-1, 1-2 and so on connecting to bit lines BL0, BL1, BL2 and so on and aligned in an array form.
The memory cell unit 1 (−0, −1, −2 and so on) has multiple (three in the example in FIG. 1) memory cells M connected in series between the selected gate transistors S and S2. The gate electrodes of the memory cells M are connected to word lines WL0, WL1 and WL2. The gate electrode of the selected gate transistor S1 is connected to a selected gate line SSL on the bit line side, and the gate electrode of the selected gate transistor S2 is connected to a selected gate line GSL on the source side.
FIG. 1 shows an example in which the word line WL1 is a selected word line, and the word lines WL0 and WL2 are unselected word lines.
Non-Patent Document 1: K.-D. Suh et al., “A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” IEEE J. Solid-State Circuits, vol. 30, pp. 1149-1156, November 1995;
Non-Patent Document 2: Y. Iwata et al., “A 35 ns Cycle Time 3.3 V Only 32 Mb NAND Flash EEPROM,” IEEE J. Solid-State Circuits, Vol. 30, pp. 1157-1164, November 1995; and
Non-Patent Document 3: J. F. Dickson, “On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique,” IEEE J. Solid-State Circuits, vol. SC-11, pp. 374-378, June 1976.